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PCF8813 Datasheet(PDF) 40 Page - NXP Semiconductors |
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PCF8813 Datasheet(HTML) 40 Page - NXP Semiconductors |
40 / 72 page 2004 Mar 05 40 Philips Semiconductors Product specification (67 + 1) × 102 pixels matrix LCD driver PCF8813 8. VLCD external voltage applied to VLCDIN and VLCDSENSE inputs; VLCDOUT disconnected; VPR and PC set to 0 (charge pump off); display load current is not transmitted to IDD. 9. Load current = 10 µA; outputs tested one at a time. 16 AC CHARACTERISTICS VDD1 = 1.7 to 3.3 V; VSS =0V; VLCD = 3.0 to 9.0 V; Tamb = −40 to +85 °C; all timings specified are based on 20% to 80% of VDD with an input voltage swing of VSS to VDD; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT fext external clock frequency note 1 20 38 65 kHz fframe frame frequency internal oscillator note 2 56 66 76 Hz note 3 62 69 76 Hz tVHRL VDD on to RES LOW time see Fig.37 0(4) − 1 µs tRW reset pulse width LOW time see Fig.37 500 −− ns tR(oper) end of reset pulse to interface operational see Fig.37 1000 −− ns 6800-type parallel bus; VDD1 = 1.8 to 3.3 V; see Figs 38 and 39 tDCSU data/command set-up time 0 − 25 ns tDCHD data/command hold time 0 −− ns TDS(cyc) data strobe cycle time 1000 −− ns tDSL data strobe LOW time 300 −− ns tDSH data strobe HIGH time 300 −− ns tRWSU read/write set-up time 0 −− ns tRWHD read/write hold time 0 −− ns tESU chip enable set-up time 0 −− ns tEHD chip enable hold time 0 −− ns tDATSU data set-up time 80 −− ns tDATHD data hold time 30 −− ns tDATACC output access time −− 280 ns tDATOH output disable time 10 − 200 ns 8080-type parallel bus; VDD1 = 1.8 to 3.3 V; see Fig.40 tDCSU data/command set-up time 0 − 25 ns tDCHD data/command hold time 0 −− ns TDS(cyc) data strobe cycle time 1000 −− ns tDSLR data strobe LOW time (read) 120 −− ns tDSLW data strobe LOW time (write) 240 −− ns tDSHR data strobe HIGH time (read) 120 −− ns tDSHW data strobe HIGH time (write) 120 −− ns tDATSU data set-up time 80 −− ns tDATHD data hold time 30 −− ns tDATACC output access time −− 280 ns tDATOH output disable time 10 − 200 ns |
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