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74LVC32ATTR Datasheet(PDF) 1 Page - STMicroelectronics |
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74LVC32ATTR Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 11 page 1/11 July 2004 s 5V TOLERANT INPUTS s HIGH SPEED: tPD = 4.2ns (MAX.) at VCC = 3V s POWER DOWN PROTECTION ON INPUTS AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V s PCI BUS LEVELS GUARANTEED AT 24 mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 3.6V (1.2V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 32 s LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) s ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LVC32A is a low voltage CMOS QUAD 2-INPUT OR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. It can be interfaced to 5V signal environment for inputs in mixed 3.3/5V system. It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LVC32A LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE HIGH PERFORMANCE Figure 1: Pin Connection And IEC Logic Symbols Table 1: Order Codes PACKAGE T & R SOP 74LVC32AMTR TSSOP 74LVC32ATTR TSSOP SOP Rev. 4 |
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