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S1T8825B01-R0B0 Datasheet(PDF) 9 Page - Samsung semiconductor |
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S1T8825B01-R0B0 Datasheet(HTML) 9 Page - Samsung semiconductor |
9 / 16 page 1.3GHZ DUAL PLL S1T8825B 9 LOCK DETECTOR OUTPUT When the phase comparator detects a phase difference, LD (Pin5) outputs “L”. When the phase comparator locks, LD outputs “H”. On standby, it outputs “H”. When T is less than 2/fosc (T<2 /fosc ) for more than three cycles of reference divider output as in the figure below, the lock detector outputs “H”. fosc: OSCI operating frequency (LOCAL OSC). T: time difference of the pulse between reference divider output and channel divider output. PROGRAMMABLE STANDBY MODE (SB1, SB2, SBR) Standby mode can be controlled by 3-control bits such as SB1, SB2 and SBR. SB1 and SB2 can control the standby mode of channel 1 and channel2. The “SBR” bit can do ON / OFF control of reference divider. Figure 3. Lock Detector Output Control Bit Standby Mode State SB1 SB2 SBR CH1 CH2 REF Mode Status 00 × ON ON ON Inter locking Mode 01 × ON OFF ON CH1 Locking Mode 10 × OFF ON ON CH2 Locking Mode 1 1 0 OFF OFF ON REF On Mode 1 1 1 OFF OFF OFF Standby Mode B A T T<2/fosc Reference Divider output Channel Divider output Charge pump output Lock detector output A = (s) B = (s) Number of divisions by reference divider fosc 2 fosc |
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