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TM893GBK32 Datasheet(PDF) 10 Page - Texas Instruments |
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TM893GBK32 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 12 page TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature ’497FBK32-60 ’893GBK32-60 ’497FBK32-70 ’893GBK32-70 ’497FBK32-80 ’893GBK32-80 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write (see Note 7) 110 130 150 ns tPC Cycle time, page-mode read or write (see Notes 7 and 8) 40 45 50 ns tRASP Pulse duration, page-mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, non-page-mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS high 10 10 10 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tWP Pulse duration, W low 10 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data before CAS low 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W-low before CAS high 10 12 15 ns tRWL Setup time, W-low before RAS high 10 12 15 ns tWCS Setup time, W-low before CAS low 0 0 0 ns tWRP Setup time, W-high before RAS low (CBR refresh only) 10 10 10 ns tCAH Hold time, column address after CAS low 10 12 15 ns tRHCP Hold time, RAS high after CAS precharge 35 40 45 ns tDH Hold time, data after CAS low 10 12 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH Hold time, W low after CAS low 10 12 15 ns tWRH Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSH Delay time, RAS low to CAS high 50 55 60 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 30 35 40 ns tRCD Delay time, RAS low to CAS low (see Note 10) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low (CBR only) 0 0 0 ns tRSH Delay time, CAS low to RAS high 10 12 15 ns tREF Refresh time interval 32 32 32 ms tT Transition time 3 30 3 30 3 30 ns NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be greater than or equal to tCP. 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to assure access time. |
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