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GD5F2GQ4RFZIS Datasheet(PDF) 14 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD5F2GQ4RFZIS Datasheet(HTML) 14 Page - GigaDevice Semiconductor (Beijing) Inc. |
14 / 57 page SPI(x1/x2/x4) NAND Flash 2G 14 7 WRITE OPERATIONS 7.1 Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to following operations that change the contents of the memory array: • Page program • OTP program/OTP protection • Block erase The WEL bit can be cleared after a reset command. Figure7-1. Write Enable Sequence Diagram Command 0 1 2 3 4 5 6 7 06H CS# SCLK SI SO High-Z 7.2 Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is also reset by following condition: • Page program • OTP program/OTP protection • Block erase Figure7-2. Write Disable Sequence Diagram Command 0 1 2 3 4 5 6 7 04H CS# SCLK SI SO High-Z |
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