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GD25B257D Datasheet(PDF) 28 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B257D Datasheet(HTML) 28 Page - GigaDevice Semiconductor (Beijing) Inc. |
28 / 92 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25B257D 28 8.9. Read Data Bytes at Higher Speed (Fast Read 0BH or 4Fast Read 0CH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-Byte address (A23-A0) and a dummy Byte, and each bit being latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency fC, on the falling edge of SCLK. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. Figure 13. Read Data Bytes at Higher Speed Sequence Diagram (ADS=0) Figure 14. Read Data Bytes at Higher Speed Sequence Diagram (ADS=1) Command 0 1 2 3 4 5 6 7 0BH CS# SCLK SI SO High-Z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address MSB 34 35 36 37 33 6 5 4 3 2 1 0 38 39 Data Out1 32 42 43 44 45 41 46 47 40 7 6 5 4 3 2 1 0 7 6 5 7 Data Out2 CS# SCLK SI SO MSB Dummy Byte Command 0 1 2 3 4 5 6 7 0BH CS# SCLK SI SO High-Z 8 9 10 36 37 38 39 3 2 1 0 31 30 29 32-bit address MSB 42 43 44 45 41 6 5 4 3 2 1 0 46 47 Data Out1 40 50 51 52 53 49 54 55 48 7 6 5 4 3 2 1 0 7 6 5 7 Data Out2 CS# SCLK SI SO MSB Dummy Byte |
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