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RTL8111B Datasheet(PDF) 5 Page - Realtek Semiconductor Corp.

Part # RTL8111B
Description  INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS APPLICATIONS
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Manufacturer  REALTEK [Realtek Semiconductor Corp.]
Direct Link  https://www.realtek.com/en/
Logo REALTEK - Realtek Semiconductor Corp.

RTL8111B Datasheet(HTML) 5 Page - Realtek Semiconductor Corp.

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RTL8111B/RTL8168B
Registers Datasheet
Integrated Gigabit Ethernet Controller for PCI Express
v
Track ID: JATR-1076-21 Rev. 1.0
List of Tables
TABLE 1. MAC REGISTERS............................................................................................................................................................2
TABLE 2. DTCCR: DUMP TALLY COUNTER COMMAND (OFFSET 0010H-0017H, RW) .................................................................4
TABLE 3. COMMAND (OFFSET 0037H, RW)...................................................................................................................................5
TABLE 4. TPPOLL: TRANSMIT PRIORITY POLLING (OFFSET 0038H, RW)......................................................................................5
TABLE 5. INTERRUPT MASK (OFFSET 003CH-003DH, RW)...........................................................................................................5
TABLE 6. INTERRUPT STATUS (OFFSET 003EH-003FH, RW).........................................................................................................6
TABLE 7. TRANSMIT CONFIGURATION (OFFSET 0040H-0043H, RW) ............................................................................................7
TABLE 8. RECEIVE CONFIGURATION (OFFSET 0044H-0047H, RW) ...............................................................................................9
TABLE 9. 9346CR: 93C46 (93C56) COMMAND (OFFSET 0050H, RW)........................................................................................11
TABLE 10. CONFIG 0 (OFFSET 0051H, RW) ................................................................................................................................12
TABLE 11. CONFIG 1 (OFFSET 0052H, RW) ................................................................................................................................12
TABLE 12. CONFIG 2 (OFFSET 0053H, RW) ................................................................................................................................13
TABLE 13. CONFIG 3 (OFFSET 0054H, RW) ................................................................................................................................13
TABLE 14. CONFIG 4 (OFFSET 0055H, RW) ................................................................................................................................14
TABLE 15. CONFIG 5 (OFFSET 0056H, RW) ................................................................................................................................14
TABLE 16. PHYAR: PHY ACCESS (OFFSET 0060H-0063H, RW) .................................................................................................14
TABLE 17. PHYSTATUS: PHY STATUS (OFFSET 006CH, R) .........................................................................................................15
TABLE 18. RMS: RECEIVE (RX) PACKET MAXIMUM SIZE (OFFSET 00DAH-00DBH, R)...............................................................15
TABLE 19. C+CR: C+ COMMAND (OFFSET 00E0H-00E1H, RW) ..................................................................................................15
TABLE 20. RDSAR: RECEIVE DESCRIPTOR START ADDRESS (OFFSET 00E4H-00EBH, RW)........................................................16
TABLE 21. MTPS: MAX TRANSMIT PACKET SIZE (OFFSET 00ECH, RW) .....................................................................................16
TABLE 22. PHY REGISTER DEFINITIONS.......................................................................................................................................17
TABLE 23. BMCR (ADDRESS 0X00) .............................................................................................................................................17
TABLE 24. BMSR (ADDRESS 0X01)..............................................................................................................................................19
TABLE 25. PHY IDENTIFIER REGISTER 1 (ADDRESS 0X02) ...........................................................................................................20
TABLE 26. PHY IDENTIFIER REGISTER 2 (ADDRESS 0X03) ...........................................................................................................20
TABLE 27. ANAR (ADDRESS 0X04)..............................................................................................................................................21
TABLE 28. ANLPAR (ADDRESS 0X05).........................................................................................................................................21
TABLE 29. ANER (ADDRESS 0X06) ..............................................................................................................................................22
TABLE 30. ANNPTR (ADDRESS 0X07).........................................................................................................................................22
TABLE 31. ANNPRR(ADDRESS 0X08) .........................................................................................................................................22
TABLE 32. GBCR (ADDRESS 0X09) ..............................................................................................................................................23
TABLE 33. GBSR (ADDRESS 0X0A)..............................................................................................................................................23
TABLE 34. GBESR (ADDRESS 0X0F)............................................................................................................................................24
TABLE 35. EEPROM CONTENTS ..................................................................................................................................................24
TABLE 36. EEPROM RELATED MAC REGISTERS.........................................................................................................................26
TABLE 37. EEPROM RELATED POWER MANAGEMENT REGISTERS..............................................................................................26
TABLE 38. PCI CONFIGURATION SPACE TABLE ............................................................................................................................27
TABLE 39. COMMAND REGISTER IN PCI CONFIGURATION SPACE .................................................................................................34
TABLE 40. STATUS REGISTER IN PCI CONFIG SPACE ....................................................................................................................35
TABLE 41. IOAR REGISTER IN PCI CONFIG SPACE.......................................................................................................................37
TABLE 42. MEMAR REGISTER IN PCI CONFIG SPACE..................................................................................................................37
TABLE 43. BMAR REGISTER IN PCI CONFIGURATION SPACE.......................................................................................................38
TABLE 44. DEFAULT VALUES AFTER EEPROM AUTOLOAD ........................................................................................................38
TABLE 45. MESSAGE CONTROL.....................................................................................................................................................50
TABLE 46. MESSAGE ADDRESS .....................................................................................................................................................50
TABLE 47. MESSAGE UPPER ADDRESS..........................................................................................................................................51
TABLE 48. MESSAGE DATA...........................................................................................................................................................51
TABLE 49. LARGE-SEND TASK OFFLOAD TX COMMAND DESCRIPTOR-1 ......................................................................................53
TABLE 50. LARGE-SEND TASK OFFLOAD TX COMMAND DESCRIPTOR-2 ......................................................................................53
TABLE 51. NORMAL TX COMMAND DESCRIPTOR-1 ......................................................................................................................55
TABLE 52. NORMAL TX COMMAND DESCRIPTOR-2 ......................................................................................................................55


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