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RTL8111B Datasheet(PDF) 57 Page - Realtek Semiconductor Corp. |
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RTL8111B Datasheet(HTML) 57 Page - Realtek Semiconductor Corp. |
57 / 75 page RTL8111B/RTL8168B Registers Datasheet Integrated Gigabit Ethernet Controller for PCI Express 51 Track ID: JATR-1076-21 Rev. 1.0 5.7.5. Message Upper Address Table 47. Message Upper Address Bits RW Field Description 31::00 RW Message Upper Address System-specified message/vector upper address. Upper 32 bits of a 64-bit message/vector address. This register is effective only when the DAC function is enabled, i.e., 64-bit addressing is enabled; bit7 in Message Control register is set. If the contents of this register are 0, the RTL8111B/RTL8168B only performs 32-bit addressing for the memory write of the messages/vectors. 5.7.6. Message Data Table 48. Message Data Bits RW Field Description 15::00 RW Message Data If the Message Enable bit is set, the message/vector data is driven onto the lower word (AD[15::0]) of the memory write transaction’s data phase. AD[31::16] are driven to zero during the memory write transaction’s data phase. C/BE[3::0]# are asserted during the data phase of the memory write transaction. |
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