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RTL8111B Datasheet(PDF) 11 Page - Realtek Semiconductor Corp. |
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RTL8111B Datasheet(HTML) 11 Page - Realtek Semiconductor Corp. |
11 / 75 page RTL8111B/RTL8168B Registers Datasheet Integrated Gigabit Ethernet Controller for PCI Express 5 Track ID: JATR-1076-21 Rev. 1.0 2.3. Command (Offset 0037h, RW) Table 3. Command (Offset 0037h, RW) Bit Symbol RW Description 7-5 - - Reserved 4 RST RW Reset: Set this bit to 1 to force the RTL8111B/RTL8168B into a software reset state which disables the transmitter and receiver, reinitializes the FIFOs, and resets the system buffer pointer to the initial value (the start address of each descriptor group set in TNPDS, THPDS, and RDSAR registers). The values of IDR0-5, MAR0-7 and PCI configuration space will have no changes. This bit is 1 during the reset operation, and is self-cleared to 0 when the reset operation is complete. 3 RE RW Receiver Enable 2 TE RW Transmitter Enable 1-0 - - Reserved 2.4. TPPoll: Transmit Priority Polling (Offset 0038h, RW) Table 4. TPPoll: Transmit Priority Polling (Offset 0038h, RW) Bit Symbol RW Description 7 HPQ W High Priority Queue polling: Writing a ‘1’ to this bit will notify the RTL8111B/RTL8168B that there is a high priority packet(s) waiting to be transmitted. The RTL8111B/RTL8168B will clear this bit automatically after all high priority packets have been transmitted. Writing a ‘0’ to this bit has no effect. 6 NPQ W Normal Priority Queue polling: Writing a ‘1’ to this bit will notify the RTL8111B/RTL8168B that there is a normal priority packet(s) waiting to be transmitted. The RTL8111B/RTL8168B will clear this bit automatically after all normal priority packets have been transmitted. Writing a ‘0’ to this bit has no effect. 5-1 - - Reserved 0 FSWInt W Forced Software Interrupt: Writing a ‘1’ to this bit will trigger an interrupt, and the SWInt bit (bit8, ISR, offset3Eh-3Fh) will set. The RTL8111B/RTL8168B will clear this bit automatically after the SWInt bit (bit8, ISR) is cleared. Writing a ‘0’ to this bit has no effect. 2.5. Interrupt Mask (Offset 003Ch-003Dh, RW) Table 5. Interrupt Mask (Offset 003Ch-003Dh, RW) Bit Symbol RW Description 15 - - Reserved 14 TimeOut RW Time Out Interrupt: 1: Enable, 0: Disable. |
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