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AM79C987 Datasheet(PDF) 5 Page - Advanced Micro Devices |
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AM79C987 Datasheet(HTML) 5 Page - Advanced Micro Devices |
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5 / 30 page  Am79C987 5 PRELIMINARY PIN DESCRIPTION CK Clock Input CK is the master 20 MHz clock. The IMR+ device X 1 pin must also be clocked with the identical clock signal. RST Reset Input, Active LOW Driving this pin LOW resets the internal logic of the HIMIB. The HIMIB device must be reset with the identi- cal synchronous RST signal of the IMR+ device. Note: None of the 32-bit and 48-bit attributes are cleared upon reset. SI Serial Input (to the IMR+ chip) Output The SI pin is used to output management port commands to the IMR+ device. This pin should be con- nected to the SI pin of the IMR+ chip. SO Serial Output (from the IMR+ chip) Input The SO pin is used to receive management port infor- mation from the IMR+ device. This pin should be connected to the SO pin of the IMR+ chip. SCLK Serial Clock Output 10 MHz clock used to drive the IMR+ management port serial clock (SCLK). CRS Carrier Sense Input The CRS pin should be connected to the CRS pin of the IMR+ device. States of the internal carrier sense signals of the IMR+ AUI and twisted-pair ports are se- rially input on this pin continuously. STR Store Output, High Impedance This pin should be connected to the STR pin of the IMR+ chip. This pin is an output when the HIMIB device is interfaced to an IMR+ device; otherwise it remains in high-impedance state. ACK Acknowledge Input, Active LOW When this input is asserted, it indicates that data on the DAT and JAM inputs are valid. COL Expansion Collision Input, Active LOW When this input is asserted, it indicates that there is a transmit collision because more than one IMR+ device is active (requesting access to the expansion port). DAT Expansion Port Data Input When ACK is asserted and JAM is LOW, the expansion port data consists of the NRZ received data. When ACK is not asserted, the state of DAT is ignored. JAM Jam Input When ACK is asserted and JAM is HIGH, an active IMR+ device is in a collision state. When JAM is as- serted, the state of DAT will indicate either a multiport (DAT = 0) or single-port (DAT = 1) collision condition. When ACK is not asserted, the state of JAM is ignored. D7–0 Data Input/Output, 3-State Data Input/Output pins. These pins are in high- impedance state if the HIMIB device is not selected. C/D Command/Data Input This input pin allows selection of either the Command or Data port in the HIMIB device. When this signal is HIGH, the Command port is selected and, when it is LOW, the Data port is selected. This pin is typically con- nected to the least significant bit of the address bus. WR Write Strobe Input, Active LOW When this pin is asserted and the CS is active, a write operation is initiated. RD Read Strobe Input, Active LOW When this pin is asserted and the CS is active, a read operation is initiated. |
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