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ADC12DL065CIVS Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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ADC12DL065CIVS Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 26 page  ADC12DL065 Dual 12-Bit, 65 MSPS, 3.3V, 360mW A/D Converter General Description The ADC12DL065 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog in- put signals into 12-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC12DL065 achieves 11.0 effective bits at nyquist and consumes just 360 mW at 65 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW. The differential inputs provide a full scale differential input swing equal to 2 times V REF with the possibility of a single- ended input. Full use of the differential input is recom- mended for optimum performance. The digital outputs from the two ADC’s are available on a single multiplexed 12-bit bus or on separate buses. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two’s comple- ment. To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL065 can be con- nected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40˚C to +85˚C. An evaluation board is available to ease the evaluation process. Features n Single +3.3V supply operation n Internal sample-and-hold n Internal reference n Outputs 2.4V to 3.6V compatible n Power down mode n Duty Cycle Stabilizer n Multiplexed Output Mode Key Specifications n Resolution 12 Bits n DNL ±0.4 LSB (typ) n SNR (f IN = 10 MHz) 69 dB (typ) n SFDR (f IN = 10 MHz) 86 dB (typ) n Data Latency 7 Clock Cycles n Power Consumption n -- Operating 360 mW (typ) n -- Power Down Mode 36 mW (typ) Applications n Ultrasound and Imaging n Instrumentation n Communications Receivers n Sonar/Radar n xDSL n Cable Modems n DSP Front Ends Connection Diagram 20100101 TRI-STATE® is a registered trademark of National Semiconductor Corporation. May 2005 © 2005 National Semiconductor Corporation DS201001 www.national.com |
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