RTL8100C & RTL8100CL
Datasheet
Single-Chip Fast Ethernet Controller
41
Track ID: JATR-1076-21 Rev. 1.06
6.3. PCI Configuration Space Status
Status: The status register is a 16-bit register used to record status information for PCI bus related events.
Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set.
Table 42. PCI Configuration Space Status
Bit
Symbol
Description
15
DPERR
Detected Parity Error.
When set indicates that the RTL8100C(L) detected a parity error, even if parity error handling is
disabled in the command register PERRSP bit.
14
SSERR
Signaled System Error.
When set indicates that the RTL8100C(L) asserted the system error pin, SERRB.
Writing a 1 clears this bit to 0.
13
RMABT
Received Master Abort.
When set indicates that the RTL8100C(L) terminated a master transaction with master abort.
Writing a 1 clears this bit to 0.
12
RTABT
Received Target Abort.
When set indicates that the RTL8100C(L) master transaction was terminated due to a target abort.
Writing a 1 clears this bit to 0.
11
STABT
Signaled Target Abort.
Set to 1 whenever the RTL8100C(L) terminates a transaction with target abort. Writing a 1 clears this
bit to 0.
10-9
DST1-0
Device Select Timing.
These bits encode the timing of DEVSELB. They are set to 01b (medium), indicating the
RTL8100C(L) will assert DEVSELB two clocks after FRAMEB is asserted.
8
DPD
Data Parity error Detected.
This bit sets when the following conditions are met:
•
The RTL8100C(L) asserts parity error(PERRB pin) or it senses the assertion of PERRB pin by
another device.
•
The RTL8100C(L) operates as a bus master for the operation that caused the error.
•
The Command register PERRSP bit is set.
Writing a 1 clears this bit to 0.
7
FBBC
Fast Back-To-Back Capable.
Config3<FbtBEn>=0, Read as 0. Write operation has no effect.
Config3<FbtBEn>=1, Read as 1.
6
UDF
User Definable Features.
Read as 0. Write operation has no effect.
The RTL8100C(L) does not support UDF.
5
66MHz
66MHz Capable.
Read as 0. Write operation has no effect.
The RTL8100C(L) has no 66MHz capability.
4
NewCap
New Capability.
Config3<PMEn>=0, Read as 0. Write operation has no effect.
Config3<PMEn>=1, Read as 1.
0-3
-
Reserved.
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