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IDT72V8985J Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT72V8985J Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 14 page 10 Commercial Temperature Range IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 Figure 7. ST-BUS® Timing F0i C4i TX RX 5707 drw10 Ch. 31, Bit 0 Ch. 0, Bit 7 Ch. 0, Bit 6 Ch. 0, Bit 6 Ch. 0, Bit 7 Ch. 31, Bit 0 Ch. 0, Bit 5 tF0iW Ch. 0, Bit 5 tF0iH tF0iS tDAA tC4i tSTiS tSTiH tCH tCL tf tr AC ELECTRICAL CHARACTERISTICS(1) ST-BUS® TIMING NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Symbol Parameter Min. Typ.(2) Max. Units Test Conditions tF0iW Frame Pulse Width 244 ns tF0iS Frame Pulse Setup Time 5 20 190 ns tF0iH Frame Pulse Hold Time 5 20 190 ns tDAA TX delay Active to Active 40 60 ns C L = 150pF tSTiS RX Setup Time 10 ns tSTiH RX Hold Time 10 ns tC4i Clock Period 244 ns tCL CK Input Low 122 ns tCH CK Input High 122 ns tr, tf Clock Rise/Fall Time 10 ns |
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