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K6R1008C1D-JI10 Datasheet(PDF) 6 Page - Samsung semiconductor |
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K6R1008C1D-JI10 Datasheet(HTML) 6 Page - Samsung semiconductor |
6 / 9 page PRELIMINARY Rev. 3.0 - 6 - July 2004 PRELIMINARY K6R1004C1D CMOS SRAM Address Data Out Previous Valid Data Valid Data TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tAA tRC tOH TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) WRITE CYCLE* * The above parameters are also guaranteed at industrial temperature range. Parameter Symbol K6R1004C1D-10 Unit Min Max Write Cycle Time tWC 10 - ns Chip Select to End of Write tCW 7- ns Address Set-up Time tAS 0- ns Address Valid to End of Write tAW 7- ns Write Pulse Width(OE High) tWP 7- ns Write Pulse Width(OE Low) tWP1 10 - ns Write Recovery Time tWR 0- ns Write to Output High-Z tWHZ 05 ns Data to Write Time Overlap tDW 5- ns Data Hold from Write Time tDH 0- ns End of Write to Output Low-Z tOW 3- ns Valid Data High-Z tRC CS Address OE Data out tHZ(3,4,5) tAA tCO tOE tOLZ tLZ(4,5) tOHZ tPU tPD 50% 50% VCC Current ICC ISB tDH |
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