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CP3SP33SMR Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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CP3SP33SMR Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 6 page 3 www.national.com 3.0 Device Overview The CP3SP33 connectivity processor is an advanced mi- crocomputer with system timing, interrupt logic, instruction cache, data memory, and I/O ports included on-chip, mak- ing it well-suited to a wide range of embedded applications. The block diagram on page 1 shows the major on-chip com- ponents of the CP3SP33. 3.1 CR16CPLUS CPU CORE The CP3SP33 contains a CR16CPlus CPU core. This core improves upon the performance of previous CP3000 devic- es by adding a 4-Kbyte instruction cache and doubling the CPU core data bus bandwidth. The cache greatly reduces instruction-fetch bandwidth on the 32-bit system bus, which leaves more bus bandwidth available for DMA-based I/O. The cache moves the average execution rate closer to the peak rate of one instruction per clock cycle, especially when executing from off-chip program memory. The DMA control- ler provides efficient sharing of the CPU core bus between the CPU and high-bandwidth peripherals such as wired and wireless communication interfaces. For information on the instruction set architecture, please refer to the CR16C Programmer’s Reference Manual (doc- ument number 424521772-101, which may be downloaded from National’s web site at http://www.national.com). 3.2 TEAK DSP CORE The Teak 16-bit fixed-point DSP core is designed for low- power, high-speed digital signal processing applications, in- cluding acoustic echo cancellation, noise reduction, and MP3/WMA decoding. It features a four-bus, dual-MAC, en- hanced Harvard architecture. The DSP has 24K bytes of dedicated program RAM, 24K bytes of data RAM, and a 4K- byte RAM shared with the CPU. The DSP has a bus master interface to the 4K-byte shared RAM and an external mem- ory bus. It also has a bus master interface to a shared audio peripheral bus. The DSP is slave on the CPU peripheral bus, for downloading software to the program RAM. The DSP has its own DMA controller for I/O and memory ac- cess. 3.3 AMBA BUS ARCHITECTURE The CPU and DSP core buses implement AMBA-compati- ble AHB high-performance 32-bit buses with bursting and split transactions. The CPU peripheral bus and CPU/DSP shared audio peripheral bus implement AMBA-compatible 32-bit APB buses. The CPU and DSP buses operate at in- dependent rates up to 96 MHz. The APB buses operate at a rate which is a factor of 1, 2, or 4 slower than the CPU AHB bus. 3.4 EXTERNAL BUS INTERFACE UNIT The External Bus Interface Unit (EBIU) provides program- mable timing, memory type, base address, size, and bus width (8, 16, or 32 bits) for three regions of up to 32M bytes. An 8-level write buffer releases the bus master to continue execution without waiting for write cycles to complete. 3.5 MEMORY The CP3SP33 devices support a uniform linear address space. Three types of on-chip memory occupy specific re- gions within this address space, along with any external memory: 32K bytes of CPU RAM 4K bytes of CPU/DSP shared RAM 8K bytes of Bluetooth sequencer and data RAM Up to 32M bytes of external memory A non-volatile external program memory is used to store the application program, Bluetooth protocol stack, and real-time operating system. The 32K bytes of CPU RAM are used for temporary storage of data and for the program stack and interrupt stack. Read and write operations can be byte-wide or word-wide, de- pending on the instruction executed by the CPU. 3.6 BLUETOOTH LLC The integrated hardware Bluetooth Lower Link Controller (LLC) complies to the Bluetooth Specification Version 1.2 and integrates the following functions: 7K-byte dedicated Bluetooth data RAM 1K-byte dedicated Bluetooth sequencer RAM Support of all Bluetooth 1.2 packet types and extended Synchronous Connection-Oriented (eSCO) links Support for fast frequency hopping of 1600 hops/s Access code correlation and slot timing recovery circuit Power Management Control Logic BlueRF-compatible interface (mode 2/3) to connect with National’s LMX5252 and other RF transceiver chips 3.7 USB The full-speed Universal Serial Bus (USB) node and host controller is compatible with USB Specification 2.0 and USB On-The-Go. It integrates the required USB transceiver, the Serial Interface Engine (SIE), and USB endpoint FIFOs. A total of seven endpoint pipes are supported: one bidirection- al pipe for the mandatory control EP0 and an additional six pipes for unidirectional endpoints to support USB interrupt, bulk, and isochronous data transfers. The on-chip USB transceiver features an integrated pullup resistor on the D+ line to UVCC. This pullup resistor can be switched in or out by the USB VBUS sense input (VBUS), which eliminates the need for external components. 3.8 CAN INTERFACE The two CAN modules support Full CAN 2.0B class, CAN serial bus interfaces for applications that require a high- speed (up to 1 Mbits per second) or a low-speed interface with CAN bus master capability. The data transfer between CAN and the CPU is established by 15 memory-mapped message buffers, which can be individually configured as receive or transmit buffers. An incoming message is filtered by two masks, one for the first 14 message buffers and an- other one for the 15th message buffer to provide a basic CAN path. A priority decoder allows any buffer to have the highest or lowest transmit priority. Remote transmission re- quests can be processed automatically by automatic recon- figuration to a receiver after transmission or by automated |
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