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K6R1016C1D-EC10 Datasheet(PDF) 5 Page - Samsung semiconductor |
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K6R1016C1D-EC10 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 9 page PRELIMINARY Rev. 3.0 - 5 - July 2004 PRELIMINARY K6R1004C1D CMOS SRAM TEST CONDITIONS Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.) Output Loads(B) DOUT 5pF* 480 Ω 255Ω for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V * Including Scope and Jig Capacitance Output Loads(A) DOUT RL = 50 Ω ZO = 50 Ω VL = 1.5V 30pF* * Capacitive Load consists of all components of the test environment. READ CYCLE* * The above parameters are also guaranteed at industrial temperature range. Parameter Symbol K6R1004C1D-10 Unit Min Max Read Cycle Time tRC 10 - ns Address Access Time tAA -10 ns Chip Select to Output tCO -10 ns Output Enable to Valid Output tOE -5 ns Chip Enable to Low-Z Output tLZ 3- ns Output Enable to Low-Z Output tOLZ 0- ns Chip Disable to High-Z Output tHZ 05 ns Output Disable to High-Z Output tOHZ 05 ns Output Hold from Address Change tOH 3- ns Chip Selection to Power Up Time tPU 0- ns Chip Selection to Power DownTime tPD -10 ns |
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