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DAC60501 Datasheet(HTML) 25 Page - Texas Instruments

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Part No. DAC60501
Description  DACx0501, 16-, 14-, 12-Bit, 1-LSB INL, Voltage-Output Digital-to-Analog Converters With Precision Internal Reference
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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DAC60501 Datasheet(HTML) 25 Page - Texas Instruments

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LEAK
BIAS
I
I
V
t
C
'
'
OUT
Q
V
C
'
25
DAC80501, DAC70501, DAC60501
www.ti.com
SBAS794 – NOVEMBER 2018
Product Folder Links: DAC80501 DAC70501 DAC60501
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Copyright © 2018, Texas Instruments Incorporated
Typical Application (continued)
9.2.1 Design Requirements
The design requirements for this circuit are as follows:
Output Range: 0-V to 5-V
Channels: 10
Output Offset Error: ±3-mV
9.2.2 Detailed Design Procedure
A basic sample-and-hold circuit consists of a voltage source (DAC in this case), a switch, a capacitor, and a
buffer. As the name implies, this circuit has two modes of operation: sample and hold. In sample mode, the
switch is closed connecting the DAC output to the hold capacitor, CH. In hold mode, the switch opens,
disconnecting the DAC output from CH. Thus, the final output is held to the sampled value because of the charge
stored on hold capacitor CH. The output buffer is needed for delivering the required current. In a practical circuit,
the switch leakage and the amplifier bias current make the capacitor drift from the stored value. Therefore, the
sample-and-hold circuit must be refreshed, even if the DAC value does not change. The key design parameters
of a sample-and-hold circuit are charge injection and voltage droop.
9.2.2.1 Charge Injection
During the sample-to-hold transition, a small amount of charge is injected onto the hold capacitor, mostly
because of the stray capacitance of the switch that creates small level changes when transitioning between
states. The resulting dc offset is typically referred to as pedestal error. This error contributes to the offset error of
the system. The pedestal error, ΔVOUT, is the measured offset voltage resulting from charge injection when the
switch transitions to hold state. ΔVOUT is related to charge injection through Equation 2.
where
Q is the injected charge coulombs
C is the value of the hold capacitor in farads
(2)
In most solid-state switch data sheets, charge injection is graphed with respect to supply voltage, analog input, or
temperature. A charge injection value of 3-pC is typical in many solid-state switches under the conditions: 25°C,
5-V supply, and 0-V analog input.
9.2.2.2 Voltage Droop
In hold mode, the voltage across CH that should have remained constant suffers a droop because of the leakage
resistance of the switch and the amplifier bias current. A simplified equation for calculating the voltage droop is
given by Equation 3
where
ILEAK is the leakage current through the switch in amperes
IBIAS is the bias current of the amplifier in amperes
C is the value of the hold capacitance in farads
(3)


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