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DAC60501 Datasheet(HTML) 8 Page - Texas Instruments

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Part No. DAC60501
Description  DACx0501, 16-, 14-, 12-Bit, 1-LSB INL, Voltage-Output Digital-to-Analog Converters With Precision Internal Reference
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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DAC60501 Datasheet(HTML) 8 Page - Texas Instruments

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8
DAC80501, DAC70501, DAC60501
SBAS794 – NOVEMBER 2018
www.ti.com
Product Folder Links: DAC80501 DAC70501 DAC60501
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Copyright © 2018, Texas Instruments Incorporated
7.6 Timing Requirements : SPI Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V, VIH
= 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V to 5.5 V, and TA = –40°C to +125°C
MIN
NOM
MAX
UNIT
fSCLK
SCLK frequency
50
MHz
tSCLKHIGH
SCLK high time
9
ns
tSCLKLOW
SCLK low time
9
ns
tSDIS
SDIN setup
5
ns
tSDIH
SDIN hold
10
ns
tCSS
SYNC to SCLK falling edge setup
13
ns
tCSH
SCLK falling edge to SYNC rising edge
10
ns
tCSHIGH
SYNC high time
15
ns
tCSIGNORE
SCLK falling edge to SYNC ignore
15
ns
tDACWAIT
Sequential DAC update wait time
1
µs
7.7 Timing Requirements : I
2C Standard Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V, VIH
= 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C
MIN
NOM
MAX
UNIT
fSCLK
SCL frequency
0.1
MHz
tBUF
Bus free time between stop and start conditions
4.7
µs
tHDSTA
Hold time after repeated start
4
µs
tSUSTA
Repeated start setup time
4.7
µs
tSUSTO
Stop condition setup time
4
µs
tHDDAT
Data hold time
0
ns
tSUDAT
Data setup time
250
ns
tLOW
SCL clock low period
4700
ns
tHIGH
SCL clock high period
4000
ns
tR
Clock and data fall time
300
ns
tF
Clock and data rise time
1000
ns
tUPDATE
Sequential DAC update wait time
1
µs
7.8 Timing Requirements : I
2C Fast Mode
All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V, VIH
= 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C
MIN
NOM
MAX
UNIT
fSCLK
SCL frequency
0.4
MHz
tBUF
Bus free time between stop and start conditions
1.3
µs
tHDSTA
Hold time after repeated start
0.6
µs
tSUSTA
Repeated start setup time
0.6
µs
tSUSTO
Stop condition setup time
0.6
µs
tHDDAT
Data hold time
0
ns
tSUDAT
Data setup time
100
ns
tLOW
SCL clock low period
1300
ns
tHIGH
SCL clock high period
600
ns
tR
Clock and data fall time
300
ns
tF
Clock and data rise time
300
ns
tUPDATE
Sequential DAC update wait time
1
µs


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