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DAC60501 Datasheet(HTML) 11 Page - Texas Instruments

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Part No. DAC60501
Description  DACx0501, 16-, 14-, 12-Bit, 1-LSB INL, Voltage-Output Digital-to-Analog Converters With Precision Internal Reference
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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DAC60501 Datasheet(HTML) 11 Page - Texas Instruments

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u
u
OUT
N
DAC_DATA
VREFIO
V
GAIN
DIV
2
R-2R
DAC
Output
DAC
Buffer
Register
DAC
Active
Register
Serial Interface
DAC Data Register
BUF
Gain
(x1 or x2)
AGND
2.5-V
Reference
VREFIO
REF Divider
(x1 or x0.5)
REF-DIV Bit
BUFF-GAIN Bit
VOUT
11
DAC80501, DAC70501, DAC60501
www.ti.com
SBAS794 – NOVEMBER 2018
Product Folder Links: DAC80501 DAC70501 DAC60501
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Copyright © 2018, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 DAC Architecture
The output channel in the DACx0501 family of devices consists of a rail-to-rail ladder architecture with an output
buffer amplifier. The devices include an internal 2.5-V reference. Figure 3 shows a block diagram of the DAC
architecture.
Figure 3. DACx0501 DAC Block Diagram
8.3.1.1 DAC Transfer Function
The input data writes to the individual DAC data registers in straight binary format. After a power-on or a reset
event, all DAC registers are set to zero code (DACx0501Z devices) or midscale code (DACx0501M devices).
The DAC transfer function is shown by Equation 1.
where:
N = resolution in bits.
Either 12 (DAC60501), 14 (DAC70501) or 16 (DAC80501).
DAC_DATA = decimal equivalent of the binary code that is loaded to the DAC register (address 8h).
DAC_DATA ranges from 0 to 2
N – 1.
VREFIO = DAC reference voltage at the VREFIO pin. Either VREFIO from the internal 2.5-V reference or
VREFIO from an external reference.
DIV = 1 (default) or 2, as set by the REF-DIV bit in the GAIN register (address 4h).
GAIN = 1 or 2 (default), as set by the BUFF-GAIN bit in the GAIN register (address 4h).
(1)
8.3.1.2 DAC Register Structure
Data written to the DAC data registers are initially stored in the DAC buffer registers. The update mode of the
DAC output is determined by the status of the DAC_SYNC_EN bit (address 2h).
In asynchronous mode (default, DAC_SYNC_EN = 0), a write to the DAC buffer register results in an immediate
update of the DAC active register. In SPI mode, the DAC output (VOUT pin) updates on the rising edge of
SYNC. In I2C mode, the DAC output (VOUT pin) updates on the falling edge of SCL on the last acknowledge bit.
In synchronous mode (DAC_SYNC_EN = 1), writing to the DAC buffer register does not automatically update the
DAC active register. Instead, the update occurs only after a software LDAC trigger event. A software LDAC
trigger generates through the LDAC bit in the TRIGGER register (address 5h). When the host reads from a DAC
buffer register, the value held in the DAC buffer register is returned (not the value held in the DAC active
register).


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