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IDT71V124S20YI Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT71V124S20YI Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 8 page 6.42 3 IDT71V124, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Revolutionary Pinout Commercial and Industrial Temperature Ranges PAR T IN OBSOLESCENCE ORDER 71V124SA FOR NEW DESIGNS 3484 drw 03 298 Ω 216 Ω 30pF DATA OUT 3.3V Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) Figure 1. AC Test Load 3484 drw 04 298 Ω 216 Ω 5pF* DATAOUT 3.3V *Including jig and scope capacitance. AC Test Conditions DC Electrical Characteristics(1) (VDD = 3.3V ± 10%, VLC = 0.2V, VHC = VDD – 0.2V) NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 71V124S15 71V124S20 Symbol Parameter Com'l. Ind. Com'l. Ind. Unit ICC Dynamic Operating Current CS < VIL, Outputs Open, VDD = Max., f = fMAX(2) 100 120 95 115 mA ISB Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open, VDD = Max., f = fMAX(2) 35 40 30 35 mA ISB1 Full Standby Power Supply Current (CMOS Level) CS > VHC, Outputs Open, VDD = Max., f = 0(2) VIN < VLC or VIN > VHC 57 5 7 mA 3484 tbl 06 Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1 and 2 3484 tbl 07 |
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