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IS41LV4100-60JI Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS41LV4100-60JI Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
1 / 19 page IS41C4100 IS41LV4100 ISSI® Integrated Silicon Solution, Inc. — 1-800-379-4774 1 PRELIMINARY INFORMATION Rev. 00A 09/10/01 This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. 1Meg x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE FEATURES • TTL compatible inputs and outputs • Refresh Interval: 1024 cycles/16 ms • Refresh Mode : RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single power supply 5V ± 10% (IS41C4100) 3.3V ± 10% (IS41LV4100) • Industrail Temperature Range -40 oC to 85oC DESCRIPTION The ISSI IS41C4100 and IS41LV4100 are 1,048,576 x 4-bit high-performance CMOS Dynamic Random Access Memory. Both products offer accelerated cycle access EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short as 10ns per 4-bit word. These features make the IS41C4100 and IS41LV4100 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C4100 and IS41LV4100 are available in a 20-pin, 300-mil SOJ package. KEY TIMING PARAMETERS Parameter -35 -60 Unit Max. RAS Access Time (tRAC) 35 60 ns Max. CAS Access Time (tCAC) 10 15 ns Max. Column Address Access Time (tAA) 18 30 ns Min. Fast Page Mode Cycle Time (tPC) 12 25 ns Min. Read/Write Cycle Time (tRC) 60 110 ns PIN DESCRIPTIONS A0-A9 Address Inputs I/O0-I/O3 Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address Strobe CAS Column Address Strobe VCC Power GND Ground NC No Connection PIN CONFIGURATION 20-Pin SOJ 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 I/O0 I/O1 WE RAS A9 A0 A1 A2 A3 Vcc GND I/O3 I/O2 CAS OE A8 A7 A6 A5 A4 PRELIMINARY INFORMATION SEPTEMBER 2001 |
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