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SA56004HDP Datasheet(PDF) 6 Page - NXP Semiconductors |
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SA56004HDP Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 23 page Philips Semiconductors Product data sheet SA56004X ±1 °C accurate, SMBus-compatible, 8-pin, remote/local digital temperature sensor with over temperature alarms 2004 Oct 06 6 SMBus INTERFACE AC ELECTRICAL CHARACTERISTICS VDD = 3.0 V to 3.6 V; Tamb = 0 °C to +125 °C; unless otherwise noted. These specifications are guaranteed by design and not tested in production. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VIH Logic input HIGH voltage for SCLK, SDATA VDD = 2.7 V to 5.5 V 2.2 – – V VIL Logic input LOW voltage for SCLK, SDATA VDD = 2.7 V to 5.5 V – – 0.8 V IOL Logic output LOW sink current ALERT, T_CRIT; VOL = 0.4 V 1.0 – – mA SDATA; VOL = 0.6 V 6.0 – – mA IOH Logic output high leakage current VOH = VDD – – 1.0 µA IIH, IIL Logic input currents VIN = VDD or GND –1.0 – 1.0 µA Ci SMBus input capacitance for SCLK, SDATA – 5 – pF SMBus digital switching characteristics The switching characteristics of the SA56004X fully meet or exceed all parameters specified in SMBus version 2.0. The following parameters specify the timing between the SCLK and SDATA signals in the SA56004X. They adhere to, but are not necessarily specified as the SMBus specifications. fSCLK SCLK operating frequency – – 400 kHz tLOW SCLK LOW time 10% to 10% 4.7 5.0 – µs tHIGH SCLK HIGH time 90% to 90% 4.0 5.0 – µs tBUF SMBus free time. Delay from SDATA stop to SDATA start 4.7 – – µs tHD:STA Hold time of start condition. Delay from SDATA start to first SCLK H-L 10% of SDATA to 90% of SCLK 4.0 – – µs tHD:DAT Hold time of data. Delay from SCLK H-L to SDATA edges – 300 – ns tSU:DAT Set-up time of data in. Delay from SDATA edges to SCLK L-H 250 – – ns tSU:STA Set-up time of repeat start condition. Delay from SCLK L-H to restart SDATA 90% to to 90% 250 – – ns tSU:STO Set-up time of stop condition. Delay from SCLK H-L to SDATA stop 90% of SCLK to 90% of SDATA 4.0 – – µs tR Rise time of SCLK and SDATA – – 1 µs tF Fall time of SCLK and SDATA – – 300 ns tOF Output fall time CL = 400 pF; IO = 3 mA – – 250 ns tTIMEOUT SMBus TIMEOUT. Low period for reset of SMBus 25 – 35 ms tBUF P S SCLK SDATA SL01204 tHD:STA SP tLOW tR tF tHD:STA tHD:DAT tHIGH tSU:DAT tSU:STA tSU:STO Figure 3. Timing measurements. |
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