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UPD75P308 Datasheet(PDF) 7 Page - NEC |
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UPD75P308 Datasheet(HTML) 7 Page - NEC |
7 / 42 page 7 µPD75P316A Input output Input/output Input/output Input/output Input/output Input/output Input Input Input Input/output Input/output Input Input Input Input/output — — — TI0 PTO0 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 INT1 INT2 KR0 to KR3 KR4 to KR7 X1, X2 XT1, XT2 RESET MD0 to MD3 VPP VDD VSS 1.2 OTHER PINS — Input Input Input Input Input Input — — — Input Input — — — Input — — — External event pulse input pin for timer/event counter. Timer/event counter output pin Clock output pin Fixed frequency output pin (for buzzer or system clock trimming) Serial clock input/output pin Serial data output pin Serial bus input/output pin Serial data input pin Serial bus input/output pin Edge-detected vectored interrupt input pin (rising or falling edge detection). Edge-detected vectored interrupt input pin (detection edge selectable) Edge-detected testable input pin (rising edge detection) Testable Input/output pins (parallel falling edge detection) Testable Input/output pins (parallel falling edge detection) Main system clock oscillation crystal/ceramic connection pins. When an external clock is used, the clock is input to X1 and the inverted clock to X2. Subsystem clock oscillation crystal connection pins When an external clock is used, the clock is input to XT1 and the inverted clock to XT2. XT1 can be used as a 1-bit input (test) pin. System reset input pin (low-level active). Mode selection pin for program memory (PROM) write/ verify. Program voltage application pin for program memory (PROM) write/verify . Connected to V DD in normal operation. Applies +12.5 V in program memory write/verify. Positive power supply pin GND potential pin Dual- Function Pin P13 P20 P22 P23 P01 P02 P03 P00 P10 P11 P12 P60 to P63 P70 to P73 — — — P30 to P33 — — — Pin Name Input/Output Function After Reset I/O Circuit Type *1 B - C E - B E - B E - B F - A F - B M - C B B - C B - C F - A F - A — — B E - B — — — S0 to S23 S24 to S31 COM0 to COM3 VLC0 to VLC2 BIAS LCDCL*2 SYNC*2 Output Output Output — — Input/output Input/output — BP0 to 7 — — — P30 P31 Segment signal output pins Segment signal output pins Common signal output pins LCD drive power supply pins External split cutting output pin External extension driver drive clock output pin External extension driver synchronization clock output pin *3 *3 *3 — High impedance Input Input G - A G - C G - B — — E - B E - B |
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