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CH
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SPHE8200A
Signal
Pin
State
Description
R_CS1_B/GPIO
69
I/O
ROM / SRAM / flash chip select #1 (first device) or GPIO
Priority selection
Function
sft_cfg1[0]=1’b1
R_CS1_B (default)
(other)
GPIO[13]
R_CS2_B/GPIO
70
I/O
ROM / SRAM / flash chip select #2 or GPIO
Priority selection
Function
sft_cfg1[1]=1’b1
R_CS2_B (default)
sft_cfg4[8:6]=3’b100
DSP FL2
(other)
GPIO[35]
R_CS3_B/GPIO
71
I/O
ROM / SRAM / flash chip select #3 or GPIO
Priority selection
Function
sft_cfg1[2]=1’b1
R_CS3_B (default)
sft_cfg4[11:9]=3’b100
DSP FLAGOUT
(other)
GPIO[36]
Crystal / Clock Pins (2)
CLKIN
78
I
Clock input / crystal in (XTALI)
CLKOUT
77
O
Clock output / crystal out (XTALO)
SDRAM Interface Pins (57)
M_DD[7]
80
I/O
SDRAM data bus [7]
M_DD[6]
81
I/O
SDRAM data bus [6]
M_DD[5]
82
I/O
SDRAM data bus [5]
M_DD[4]
83
I/O
SDRAM data bus [4]
M_DD[3]
84
I/O
SDRAM data bus [3]
M_DD[2]
86
I/O
SDRAM data bus [2]
M_DD[1]
87
I/O
SDRAM data bus [1]
M_DD[0]
88
I/O
SDRAM data bus [0]
M_WE_B
89
O
SDRAM write enable / row precharge
M_CAS_B
91
O
SDRAM column address strobe
M_RAS_B
92
O
SDRAM row address strobe / precharge
M_CS_B
93
O
SDRAM chip select
M_BA0
94
O
SDRAM bank select address [0]
M_DD[15]
96
I/O
SDRAM data bus [15]
M_DD[14]
97
I/O
SDRAM data bus [14]
M_DD[13]
98
I/O
SDRAM data bus [13]
M_DD[12]
99
I/O
SDRAM data bus [12]
M_DD[11]
101
I/O
SDRAM data bus [11]
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
11
OCT. 07, 2003
Preliminary Version: 0.2
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