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ISPLSI5128VE Datasheet(PDF) 15 Page - Lattice Semiconductor |
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ISPLSI5128VE Datasheet(HTML) 15 Page - Lattice Semiconductor |
15 / 21 page Specifications ispLSI 5128VE 15 Internal Timing Parameters Over Recommended Operating Conditions In/Out Delays tin Input Buffer Delay – 0.9 – 1.3 – 2.3 – 2.3 ns tgclk_in Global Clock Buffer Input Delay (clk0) – 1.0 – 1.3 – 1.8 – 1.8 ns trst Global Reset Pin Delay – 4.4 – 6.6 – 7.1 – 7.1 ns tgoe Global OE Pin Delay – 2.5 – 3.9 – 5.9 – 7.4 ns tbuf Output Buffer Delay – 1.1 – 2.2 – 2.7 – 3.7 ns ten Output Enable Delay – 1.0 – 1.6 – 1.6 – 1.6 ns tdis Output Disable Delay – 1.0 – 1.6 – 1.6 – 1.6 ns Routing/GLB Delays troute GRP and Logic Delay – 2.7 – 3.6 – 4.0 – 4.5 ns tpdb 5-pt Bypass Propagation Delay – 0.3 – 0.4 – 1.0 – 1.5 ns tpdi Combinatorial Propagation Delay – 1.0 – 0.0 – 0.0 – 0.0 ns tptsa Product Term Sharing Array – 1.3 – 2.4 – 3.0 – 4.5 ns tfbk Internal Feedback Delay – 0.0 – 0.0 – 0.0 – 0.5 ns tinreg Input Buffer to Macrocell Register Delay – 2.0 – 2.5 – 2.5 – 3.5 ns Register/Latch Delays ts Register Setup Time 0.6 – 1.0 – 1.5 – 1.5 – ns ts_pt Register Setup Time (Product Term Clock) 0.6 – 1.0 – 1.5 – 1.5 – ns th Register Hold Time 2.4 – 3.0 – 4.0 – 5.0 – ns tcoi Register Clock to GLB Output Delay – 0.9 – 1.0 – 1.5 – 1.5 ns tsl Latch Setup Time 0.6 – 1.0 – 1.5 – 1.5 – ns thl Latch Hold Time 2.4 – 3.0 – 4.0 – 5.0 – ns tgoi Latch Gate to GLB Output Delay – 0.9 – 1.0 – 1.5 – 1.5 ns tpdli GLB Latch propagation Delay – 1.0 – 1.5 – 2.0 – 2.5 ns tces Clock Enable Setup Time 4.1 – 4.3 – 5.3 – 6.3 – ns tceh Clock Enable Hold Time 0.3 – 1.7 – 2.7 – 3.7 – ns tsri Asynchronous Set/Reset to GLB Output Delay – 0.5 – 1.2 – 1.7 – 2.2 ns tsrr Asynchronous Set/Reset Recovery Time 1.1 – 1.2 – 1.2 – 2.2 – ns Control Delays tptclk Macrocell PT Clock Delay – 0.4 – 0.4 – 0.5 – 0.5 ns tbclk Block PT Clock Delay – 1.4 – 1.9 – 2.5 – 2.5 ns tptsr Macrocell PT Set/Reset Delay – 1.8 – 3.7 – 4.8 – 4.8 ns tbsr Block PT Set/Reset Delay – 2.8 – 5.7 – 6.8 – 6.8 ns tptoe Macrocell PT OE Delay – 1.4 – 2.0 – 2.1 – 3.6 ns tgptoe Global PT OE Delay – 2.4 – 7.5 – 7.6 – 8.6 ns -180 -125 -100 -80 MIN MAX MIN MAX MIN MAX MIN MAX UNIT PARAMETER DESCRIPTION Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. Timing v.2.0 |
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