ADP3181JRQZ-RL datasheet(10/24 Pages) AD

Part #	ADP3181JRQZ-RL

Description	5-Bit or 6-Bit Programmable 2-,3-,4-Phase Synchronous Buck Controller

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Manufacturer	AD [Analog Devices]

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ADP3181

Rev. A | Page 10 of 24

MASTER CLOCK FREQUENCY

The clock frequency of the ADP3181 is set with an external

resistor connected from the RT pin to ground. The frequency

follows the graph in Figure 6. To determine the frequency per

phase, the clock is divided by the number of phases in use. If

PWM4 is grounded, then divide the master clock by 3 for the

frequency of the remaining phases. If PWM3 and 4 are

grounded, then divide by 2. If all phases are in use, divide by 4.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3181 combines differential sensing with a high

accuracy VID DAC and reference and a low offset error

amplifier to maintain a worst-case specification of ±14.5 mV

differential sensing error over its full operating output voltage

and temperature range. The output voltage is sensed between

the FB and FBRTN pins. FB should be connected through a

resistor to the regulation point, usually the remote sense pin of

the microprocessor. FBRTN should be connected directly to the

remote sense ground point. The internal VID DAC and

precision reference are referenced to FBRTN, which has a

minimal current of 100 μA to allow accurate remote sensing.

The internal error amplifier compares the output of the DAC to

the FB pin to regulate the output voltage.

OUTPUT CURRENT SENSING

The ADP3181 provides a dedicated current sense amplifier

(CSA) to monitor the total output current for proper voltage

positioning versus load current and for current limit detection.

Sensing the load current at the output gives the total average

current being delivered to the load, which is an inherently more

accurate method then peak current detection or sampling the

current across a sense element such as the low side MOSFET.

This amplifier can be configured several ways depending on the

objectives of the system:

•

Output inductor ESR sensing without a thermistor for

lowest cost.

•

Output inductor ESR sensing with a thermistor for

improved accuracy with tracking of inductor temperature.

•

Sense resistors for highest accuracy measurements.

The positive input of the CSA is connected to the CSREF pin,

which is connected to the output voltage. The inputs to the

amplifier are summed together through resistors from the

sensing element (such as the switch node side of the output

inductors) to the inverting input, CSSUM. The feedback resistor

between CSCOMP and CSSUM sets the gain of the amplifier,

and a filter capacitor is placed in parallel with this resistor. The

gain of the amplifier is programmable by adjusting the feedback

resistor to set the load line required by the microprocessor. The

current information is then given as the difference of CSREF –

CSCOMP. This difference signal is used internally to offset the

VID DAC for voltage positioning and as a differential input for

the current limit comparator.

To provide the best accuracy for the sensing of current, the CSA

has been designed to have a low offset input voltage. Also, the

sensing gain is determined by external resistors so that it can be

made extremely accurate.

ACTIVE IMPEDANCE CONTROL MODE

For controlling the dynamic output voltage droop as a function

of output current, a signal proportional to the total output cur-

rent at the CSCOMP pin can be scaled to be equal to the droop

impedance of the regulator times the output current. This

droop voltage is then used to set the input control voltage to the

system. The droop voltage is subtracted from the DAC refer-

ence input voltage directly to tell the error amplifier where the

output voltage should be. This differs from previous implemen-

tations and allows enhanced feed-forward response.

CURRENT CONTROL MODE AND THERMAL

BALANCE

The ADP3181 has individual inputs for each phase, which are

used for monitoring the current in each phase. This informa-

tion is combined with an internal ramp to create a current

balancing feedback system that has been optimized for initial

current balance accuracy and dynamic thermal balancing

during operation. This current balance information is indepen-

dent of the average output current information used for

positioning described previously.

The magnitude of the internal ramp can be set to optimize

the transient response of the system. It also monitors the supply

voltage for feed-forward control for changes in the supply.

A resistor connected from the power input voltage to the

RAMPADJ pin determines the slope of the internal PWM

ramp. Detailed information about programming the ramp is

given in the Applications section.

External resistors can be placed in series with individual phases

to create an intentional current imbalance, such as when one

phase may have better cooling and can support higher currents.

Resistors RSW1 through RSW4 (see the typical application cir-

cuit in Figure 10) can be used for adjusting thermal balance. It

is best to have the ability to add these resistors during the initial

design, so make sure placeholders are provided in the layout.

To increase the current in any phase, make RSW for that phase

larger (make RSW = 0 for the hottest phase; do not change

during balancing). Increasing RSW to only 500 Ω makes a

substantial increase in phase current. Increase each RSW value by

small amounts to achieve balance, starting with the coolest

phase first.

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ADP3181JRQZ-RL Datasheet(PDF) 10 Page - Analog Devices

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