Approval Sheet

Page 9 of 16

ASC_RMASME494ATF03_V03

Sep.2017

Table 10. Digital Interface Timing Specifications

Parameter

Symbol

Condition

Min.

Max.

Unit

Data Setup Time (Note 1)

See the Figure 6, input Tr/Tf = 3.5 to 6.5ns

1

-

ns

Data Hold Time (Note 1)

See the Figure 6, input Tr/Tf = 3.5 to 6.5ns

5

-

ns

Time for Data Output Valid from

SCLK rising edge (Note 2)

Half Speed Read

See the Figure 6 and 7, input Tr/Tf = 3.5 to 10ns

0

22

ns

SDATA Output Transition

(Rise/Fall) Time

Half Speed Read

See the Figure 6 and 7, input Tr/Tf = 3.5 to 10ns

2.1

10

ns

Data Drive Release Time

Half Speed Read

See the Figure 6 and 7, input Tr/Tf = 3.5 to 10ns

-

18

ns

Vio Supply Rise Time

See the Figure 8

-

400

μs

RFFE I/O Voltage Reset Timing

See the Figure 8

10

-

μs

Signal Reset Delay Time

See the Figure 8

120

-

μs

RF Switching Time

See the Figure 9

-

5

μs

Switching Interval (Note 3)

See the Figure 9

20

-

μs

Startup Time (Note 4)

See the Figure 4

-

20

μs

Note 1 : Input SDATA is sampled at the falling edge of the SCLK.

Note 2 : Output SDATA changes at the rising edge of the SCLK.

Note 3 : The time between the consecutive Register Write Command Sequences for the Switch State register.

Note 4 : The time for the switch to reach Active State.

Note : The table of input SCLK signal conditions as below.

Parameter

Symbol

Ratings

Unit

SCLK Frequency

Full Speed

0.032 to 26

MHz

Half Speed

0.032 to 13

SCLK Period

Full Speed

0.038 to 32

μs

Half Speed

0.077 to 32

SCLK Rise/Fall Time

Full/Half Speed

3.5 to 6.5

ns

SCLK Input Duty Cycle,

High/Low Time

50

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