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ST25E64EM1TR Datasheet(PDF) 3 Page - STMicroelectronics |
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ST25E64EM1TR Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 16 page Mode RW bit Bytes Initial Sequence Current Address Read ’1’ 1 START, Device Select, RW = ’1’ Random Address Read ’0’ 1 START, Device Select, RW = ’0’, Address, ’1’ reSTART, Device Select, RW = ’1’ Sequential Read ’1’ 1 to 8192 As CURRENT or RANDOM Mode Byte Write ’0’ 1 START, Device Select, RW = ’0’ Page Write ’0’ 32 START, Device Select, RW = ’0’ Table 4. Operating Modes Device Code Chip Enable RW Bit b7 b6 b5 b4 b3 b2 b1 b0 Device Select 1 0 1 0 E2 E1 E0 RW Note: The MSB b7 is sent first. Table 3. Device Select Code When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condi- tion. In this way, up to 8 ST24/25E64 may be connected to the same I2C bus and selected indi- vidually, allowing a total addressing field of 512 Kbit. Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Untill the VCC voltage has reached the POR threshold value, the internal reset is active: all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. SIGNALS DESCRIPTION Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3) Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. Aresistor must be connectedfrom the SDA bus line to VCC to act as pull up (see Figure 3). Chip Enable (E0 - E2). These chip enable inputs are used to set the 3 least significant bits of the 7 bit device select code. They may be driven dynami- cally or tied to VCC or VSS to establish the device select code. Note that the VIL and VIH levels for the inputs are CMOS, not TTL compatible. Write Control (WC). The Write Control feature WC is useful to protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC at VIH)or disable (WC at VIL) the internal write protection. When pin WC is unconnected, the WC input is internally read as VIL (see Table 5). When WC = ’1’, Device Select and Address bytes are acknowledged; Data bytes are not acknow- ledged. Refer to the AN404 Application Note for more de- tailed information about Write Control feature. 3/16 ST24E64, ST25E64 |
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