MC10EP29, MC100EP29

http://onsemi.com

7

0

100

200

300

400

500

600

700

800

900

0

1000

2000

3000

4000

5000

FREQUENCY (MHz)

1

2

3

4

5

6

7

8

9

(JITTER)

V TT = V CC – 2.0 V

Figure 3. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020 – Termination of ECL Logic Devices.)

W

Driver

Device

Receiver

Device

QD

50

W

50

V TT

Q

D

Resource Reference of Application Notes

AN1404

–

AN1405

–

ECL Clock Distribution Techniques

AN1406

–

Designing with PECL (ECL at +5.0 V)

AN1504

–

Metastability and the ECLinPS Family

AN1568

–

Interfacing Between LVDS and ECL

AN1650

–

Using Wire–OR Ties in ECLinPS Designs

AN1672

–

The ECL Translator Guide

AND8001

–

Odd Number Counters Design

AND8002

–

Marking and Date Codes

AND8009

–

ECLinPS Plus Spice I/O Model Kit

AND8020

–

Termination of ECL Logic Devices

For an updated list of Application Notes, please see our website at http://onsemi.com.