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IDT74ALVC125PY Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT74ALVC125PY Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 6 page  5 INDUSTRIALTEMPERATURERANGE IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE Open VLOAD GN D VCC Pulse Generator D.U.T. 500 Ω 500 Ω C L RT VIN VOUT (1, 2) ALV C L ink IN PU T VIH 0V VOH VOL tPLH1 tSK (x) OU TPU T 1 OU TPU T 2 tPHL1 tSK (x) tPLH2 tPHL2 VT VT VOH VT VOL tSK(x) = tPLH2 - tPLH1 or tPH L2 - tPHL1 ALV C L ink SAM E PHASE IN PU T TR AN SITION OPPOSITE PHASE IN PU T TR AN SITION 0V 0V VOH VOL tPLH tPHL tPHL tPLH OU TPU T VIH VT VT VIH VT ALV C L ink DATA IN PU T 0V 0V 0V 0V tREM TIM ING IN PU T SYNCHRONOUS CONTROL tSU tH tSU tH VIH VT VIH VT VIH VT VIH VT ALV C L ink ASYN CH RON OU S CONTROL LO W -H IGH -LOW PULSE H IGH -LOW -H IGH PULSE VT tW VT ALV C Link CONTROL IN PU T tPLZ 0V OU TPU T NORMALLY LO W tPZH 0V SW ITCH CLO SED OU TPU T NORMALLY HIGH ENABLE D ISABLE SW ITCH OPEN tPHZ 0V VLZ VOH VT VT tPZL VLOAD/2 VLOAD/2 VIH VT VOL VHZ ALV C L ink TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES SET-UP, HOLD, AND RELEASE TIMES SWITCH POSITION OUTPUT SKEW - TSK (x) DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. PULSE WIDTH Symbol VCC(1)= 3.3V ± 0.3V VCC(1) = 2.7V VCC(2)= 2.5V ± 0.2V Unit VLOAD 66 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF ALVC QUAD Link Test Switch Open Drain Disable Low Enable Low VLOAD Disable High Enable High GND All Other tests Open ALVC QUAD Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. |
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