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MAX9288GTMVY+ Datasheet(PDF) 60 Page - Maxim Integrated Products |
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MAX9288GTMVY+ Datasheet(HTML) 60 Page - Maxim Integrated Products |
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60 / 103 page  MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 60 Figure 41 shows the UART protocol for writing and reading in base mode between the µC and the serializer/deserializer. Figure 42 shows the UART data format. Even parity is used. Figure 43 and Figure 44 detail the formats of the SYNC byte (0x79) and the ACK byte (0xC3). The µC and the connected slave chip generate the SYNC byte and ACK byte, respectively. Events such as device wake-up and GPI generate transitions on the control channel that can be ignored by the µC. Data written to the deserial- izer registers do not take effect until after the ACK byte is sent. This allows the µC to verify that write commands are received without error, even if the result of the write command directly affects the serial link. The slave uses the SYNC byte to synchronize with the host UART’s data rate. If the GPI or MS inputs of the deserializer toggle while there is control-channel communication, or if a line fault occurs, the control-channel communication is corrupted. In the event of a missed or delayed acknowledge (~1ms due to control channel timeout), the µC should assume there was an error in the packet transmission or response. In base mode, the µC must keep the UART Tx/Rx lines high no more than four bit times between bytes in a packet. Keep the UART Tx/Rx lines high for at least 16 bit times before starting to send a new packet. Figure 41. GMSL UART Protocol for Base Mode Figure 42. GMSL UART Data Format for Base Mode Figure 43. SYNC Byte (0x79) Figure 44. ACK Byte (0xC3) WRITE DATA FORMAT SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1 BYTE N ACK BYTE N BYTE 1 ACK MASTER READS FROM SLAVE READ DATA FORMAT MASTER WRITES TO SLAVE MASTER WRITES TO SLAVE MASTER READS FROM SLAVE START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP 1 UART FRAME FRAME 1 FRAME 2 FRAME 3 STOP START STOP START START D0 1 0 0 1 1 1 1 0 D1 D2 D3 D4 D5 D6 D7 PARITYSTOP START D0 1 1 0 0 0 0 1 1 D1 D2 D3 D4 D5 D6 D7 PARITY STOP |
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