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MAX9288GTMVY+ Datasheet(PDF) 92 Page - Maxim Integrated Products |
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MAX9288GTMVY+ Datasheet(HTML) 92 Page - Maxim Integrated Products |
92 / 103 page MAX9288/MAX9290 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output www.maximintegrated.com Maxim Integrated │ 92 Table 25. Register Table (continued) REGISTER ADDRESS BITS NAME VALUE FUNCTION DEFAULT VALUE 0x12 D7 MCLKSRC 0 MCLK derived from PCLKOUT. See Table 9. 0 1 MCLK derived from internal oscillator. D[6:0] MCLKDIV 0000000 MCLK disabled. 0000000 XXXXXXX MCLK divider. 0x13 D[7:0] — 0X000000 Reserved 0X000000 0x14 D7 INVVS 0 Normal VSYNC operation. 0 1 Invert VSYNC. D6 INVHS 0 Normal HSYNC operation. 0 1 Invert HSYNC. D5 INVDE 0 Normal DE operation. 0 1 Invert DE. D4 DRS 0 High data rate mode. Power-up default when DRS pin is low (transitions on the DRS pin override the DRS bit setting). 0, 1 1 Low data rate mode. Power-up default when DRS pin is high (transitions on the DRS pin override the DRS bit setting). D3 DCS 0 Normal parallel output driver current. 0 1 Boosted parallel output driver current. D2 DISRWAKE 0 Enable remote wake-up. 0 1 Disable remote wake-up. D1 — 0 Reserved 0 D0 INTOUT 0 Drive INTOUT low. 0 1 Drive INTOUT high. |
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