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MC100ES6139DW Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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MC100ES6139DW Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 12 page Advanced Clock Drivers Device Data Freescale Semiconductor 5 MC100ES6139 Figure 5. Typical Termination for Output Driver and Device Evaluation Table 6. AC Characteristics (VCC = 0 V, VEE = –3.8 V to –3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)(1) 1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC –2.0 V. Symbol Characteristic –40 °C25°C85°C Unit Min Typ Max Min Typ Max Min Typ Max fmax Maximum Frequency > 1 > 1 > 1 GHz tPLH, tPHL Propagation Delay CLK, Q (Diff) MR, Q 550 400 850 850 550 400 850 850 550 400 850 850 ps tRR Reset Recovery 200 100 200 100 200 100 ps ts Setup Time EN, CLK DIVSEL, CLK 200 400 120 180 200 400 120 180 200 400 120 180 ps th Hold Time CLK, EN CLK, DIVSEL 100 200 50 140 100 200 50 140 100 200 50 140 ps tPW Minimum Pulse Width MR 550 450 550 450 550 450 ps tSKEW Within Device Skew Q, Q Q, Q @ Same Frequency Device-to-Device Skew(2) 2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 100 50 300 100 50 300 100 50 300 ps tJITTER Cycle-to-Cycle Jitter (RSM 1 σ) 111 ps VPP Input Voltage Swing (Differential) 200 1200 200 1200 200 1200 mV VCMR Differential Cross Point Voltage VEE+0.2 VCC–1.2 VEE+0.2 VCC–1.2 VEE+0.2 VCC–1.2 V tr tf Output Rise/Fall Times Q, Q (20% – 80%) 50 300 50 300 50 300 ps Driver Device Receiver Device QD 50 Ω Q D 50 Ω VTT VTT = VCC –- 2.0 V |
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