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74AUP1G79GM Datasheet(PDF) 11 Page - NXP Semiconductors |
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74AUP1G79GM Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 9397 750 14682 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 12 September 2005 11 of 20 Philips Semiconductors 74AUP1G79 Low-power D-type flip-flop; positive-edge trigger [1] All typical values are measured at nominal VCC. [2] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(C L × VCC 2 × f o) = sum of the outputs. [3] The condition is VI = GND to VCC. tW CP pulse width HIGH or LOW see Figure 6 VCC = 0.8 V ---ns VCC = 1.1 V to 1.3 V - 2.4 - ns VCC = 1.4 V to 1.6 V - 1.3 - ns VCC = 1.65 V to 1.95 V - 0.9 - ns VCC = 2.3 V to 2.7 V - 0.7 - ns VCC = 3.0 V to 3.6 V - 0.6 - ns CPD power dissipation capacitance f = 10 MHz [2] [3] VCC = 0.8 V - 2.2 - pF VCC = 1.1 V to 1.3 V - 2.2 - pF VCC = 1.4 V to 1.6 V - 2.2 - pF VCC = 1.65 V to 1.95 V - 2.3 - pF VCC = 2.3 V to 2.7 V - 2.6 - pF VCC = 3.0 V to 3.6 V - 3.0 - pF Table 9: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7 Symbol Parameter Conditions Min Typ [1] Max Unit |
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