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UPD720113GK-9EU-A Datasheet(PDF) 10 Page - NEC |
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UPD720113GK-9EU-A Datasheet(HTML) 10 Page - NEC |
10 / 32 page Data Sheet S16618EJ3V0DS 10 µPD720113 Recommended Operating Ranges Parameter Symbol Condition MIN. TYP. MAX. Unit Operating voltage VDD33 3.3 V for VDD33 pins 3.14 3.30 3.46 V VDD25 2.5 V for VDD25 pins 2.3 2.5 2.7 V AVDD 2.5 V for AVDD pins 2.3 2.5 2.7 V High-level input voltage VIH 2.5 V High-level input voltage 1.7 VDD25 V 3.3 V High-level input voltage 2.0 VDD33 V 5.0 V High-level input voltage 2.0 5.5 V Low-level input voltage VIL 2.5 V Low-level input voltage 0 0.7 V 3.3 V Low-level input voltage 0 0.8 V 5.0 V Low-level input voltage 0 0.8 V Hysteresis voltage VH 5 V Hysteresis voltage 0.3 1.5 V 3.3 V Hysteresis voltage 0.2 1.0 V Input rise time for SYSRSTB trst 10 ms Input rise time tri Normal buffer 0 200 ns Schmitt buffer 0 10 ms Input fall time tfi Normal buffer 0 200 ns Schmitt buffer 0 10 ms Two power supply rails limitation. The µPD720113 has two power supply rails (2.5 V, 3.3 V). The system will require the time when power supply rail is stable at VDD level. And, there will be difference between the time of VDD25 and VDD33. The µPD720113 requires that VDD25 should be stable before VDD33 becomes stable. At any case, the system must ensure that the absolute maximum ratings for VI /VO are not exceeded. System reset signaling should be asserted more than specified time after both VDD25 and VDD33 are stable. |
Similar Part No. - UPD720113GK-9EU-A |
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Similar Description - UPD720113GK-9EU-A |
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