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MC100EP809FAR2 Datasheet(PDF) 2 Page - ON Semiconductor

Part No. MC100EP809FAR2
Description  3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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 2 page
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MC100EP809
http://onsemi.com
2
** Pins will default HIGH when left open.
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
1234
5678
24
23
22
21
20
19
18
17
16
0
1
All VCCI, VCCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (VCCI 0 VCCO).
FUNCTION TABLE
OE*
L
L
H
H
PIN DESCRIPTION
FUNCTION
HSTL or LVDS Differential Inputs
LVPECL Differential Inputs
LVCMOS/LVTTL Input CLK Select
LVCMOS/LVTTL Output Enable
HSTL Differential Outputs
Positive Supply_Core (3.0 V – 3.6 V)
Positive Supply_HSTL Outputs
(1.6 V – 2.0 V)
Ground
PIN
HSTL_CLK*, HSTL_CLK**
LVPECL_CLK*, LVPECL_CLK**
CLK_SEL**
OE**
Q0–Q8, Q0–Q8
VCCI
VCCO
GND
Figure 1. 32–Lead LQFP Pinout (Top View)
Figure 2. Logic Diagram
Q2
VCCO
Q2
Q1
Q1
Q0
Q0
VCCO
VCCO
Q6
Q6
Q7
Q7
Q8
Q8
VCCO
CLK_SEL
HSTL_CLK
HSTL_CLK
LVPECL_CLK
LVPECL_CLK
OE
Q0–Q8 (HSTL)
Q0–Q8 (HSTL)
Q
D
9
9
CLK_SEL
L
H
L
H
Q0–Q8
Q0–Q8
L
L
HSTL_CLK
LVPECL_CLK
H
H
HSTL_CLK
LVPECL_CLK
* The OE (Output Enable) signal is synchronized with the
rising edge of the HSTL_CLK and LVPECL_CLK signal.
MC100EP809
* Pins will default LOW when left open.
VCCI
GND
VCCO




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