Electronic Components Datasheet Search |
|
CAT24WC164LE-1.8TE13 Datasheet(PDF) 5 Page - Catalyst Semiconductor |
|
CAT24WC164LE-1.8TE13 Datasheet(HTML) 5 Page - Catalyst Semiconductor |
5 / 10 page CAT24WC164 5 Doc. No. 1026, Rev. I address pins (A0, A1and A2) can be left floating or connected to VSS. The CAT24WC164 can be made compatible with the CAT24WC16 by tying A2, A1 and A0 to VSS or by leaving A2, A1 and A0 float. WP: Write Protect If the WP pin is tied to VCC the entire memory array becomes Write Protected (READ only). When the WP pin is tied to VSS or left floating normal read/write operations are allowed to the device. I2C BUS PROTOCOL The following defines the features of the I2C bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC164 monitor the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The most significant bit of the 8-bit slave address is fixed as 1. (see Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device or which part of the device the Master is accessing (The A1 bit must be the compliment of the A1 input pin signal). Up to eight CAT24WC164 devices may be individually addressed by the system. The next three bits are used as the three most significant bits of the data word address. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24WC164 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24WC164 then performs a Read or Write operation depending on the state of the R/ W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowl- edging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24WC164 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. Figure 4. Acknowledge Timing ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER |
Similar Part No. - CAT24WC164LE-1.8TE13 |
|
Similar Description - CAT24WC164LE-1.8TE13 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |