Revision 2.1
Jan.
2004
1
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
BS616LV4018EC
BS616LV4018EI
R0201-BS616LV4018
POWER DISSIPATION
SPEED
( ns )
STANDBY
( I CCSB1 , Max )
( I CC , Max )
PRODUCT FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
55ns:4.5~5.5V
5.0V
Vcc = 5.0V
PKG TYPE
BS616LV4018DC
DICE
BS616LV4018EC
TSOP2-44
BS616LV4018AC
BGA-48-0608
+0
O C to +70O C
4.5V ~ 5.5V
55 / 70
30uA
63mA
BS616LV4018DI
DICE
BS616LV4018EI
TSOP2-44
BS616LV4018AI
BGA-48-0608
-40
O C to +85OC
4.5V ~ 5.5V
55 / 70
60uA
65mA
Very Low Power/Voltage CMOS SRAM
256K X 16 bit
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 63mA (@55ns) operating current
I -grade: 65mA (@55ns) operating current
C-grade: 53mA (@70ns) operating current
I -grade: 55mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
The BS616LV4018 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
2.0uA at 5.0V/25oC and maximum access time of 55ns at 5.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
The BS616LV4018 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4018 is available in DICE form , JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
DESCRIPTION
FEATURES
Row
Decoder
Memory Array
2048 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A9 A8 A7
Data
Buffer
Input
Control
Gnd
Vcc
OE
WE
CE
DQ15
DQ0
A0
A13
A14
A15
A1
A2
16
16
16
16
14
128
2048
BLOCK DIAGRAM
2048
22
A17
A16
A10
A12
A6
A11
A3
Address
Input
Buffer
A5
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
BS616LV4018
A4
BSI
Operating
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
Vcc =
Vcc = 5.0V
53mA
55mA
55ns
70ns
70ns:4.5~5.5V
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