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CAT5269WI-00TE13 Datasheet(PDF) 5 Page - Catalyst Semiconductor |
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CAT5269WI-00TE13 Datasheet(HTML) 5 Page - Catalyst Semiconductor |
5 / 15 page 5 CAT5269 Document No. 2123, Rev. B POWER UP TIMING (1)(2) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. tHIGH SCL SDA IN SDA OUT tLOW tF tLOW tR tBUF tSU:STO tSU:DAT tHD:DAT tHD:STA tSU:STA tAA tDH Figure 1. Bus Timing Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method NEND(1) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR(1) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH(1) Latch-Up 100 mA JEDEC Standard 17 XDCP TIMING Symbol Parameter Min Max Units tWRPO Wiper Response Time After Power Supply Stable 5 10 µs tWRL Wiper Response Time After Instruction Issued 5 10 µs WRITE CYCLE LIMITS Symbol Parameter Max. Units tWR Write Cycle Time 5 ms |
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