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BS616LV2019TC Datasheet(PDF) 2 Page - Brilliance Semiconductor |
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BS616LV2019TC Datasheet(HTML) 2 Page - Brilliance Semiconductor |
2 / 10 page Revision 1.2 May 2004 2 R0201-BS616LV2019 PIN DESCRIPTIONS BSI BS616LV2019 Name Function A0-A16 Address Input These 17 address inputs select one of the 131,072 x 16-bit words in the RAM. CE Chip Enable 1 Input WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. DQ0 - DQ15 Data Input/Output Ports These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE CE2 Chip Enable 2 Input CE is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. (48B BGA ignore CE2 pin) 1. 48B BGA ignore CE2 condition. MODE CE CE2 (1) WE OE LB UB D0~D7 D8~D15 Vcc CURRENT H X X X X X High Z High Z ICCSB , ICCSB1 Not selected (Power Down) X L X X X X High Z High Z ICCSB , ICCSB1 Output Disabled L H H H X X High Z High Z ICC L L Dout Dout ICC H L High Z Dout ICC Read L H H L L H Dout High Z ICC LL Din Din ICC HL X Din ICC Write L H L X LH Din X ICC ICCSB , ICCSB1 X X XX H H High Z High Z |
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