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BS616UV4016DC Datasheet(PDF) 8 Page - Brilliance Semiconductor

Part # BS616UV4016DC
Description  Ultra Low Power/High Speed CMOS SRAM 256K X 16 Bit
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Manufacturer  BSI [Brilliance Semiconductor]
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BS616UV4016DC Datasheet(HTML) 8 Page - Brilliance Semiconductor

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BSI
BS616UV4016
8
R0201-BS616UV4016
Revision
1.3
Sep.
2005
WRITE CYCLE 2
(1,6)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be
active to initiate a write and any one signal can terminate a write by going inactive. The data input
setup and hold timing should be referenced to the second transition edge of the signal that terminates
the write.
3. tWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, IO pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition,
output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, IO pins are in the output state. Then the data input signals of opposite
phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.tCW is measured from the later of CE going low to the end of write.
tWC
tCW
(11)
tWP
(2)
tAW
tWHZ
(4,10)
tAS
tWR
(3)
tDH
tDW
DIN
DOUT
WE
LB, UB
CE
ADDRESS
(5)
tOW
(7)
(8)
(8,9)
tBW


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