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P8XC151SA Datasheet(PDF) 9 Page - Intel Corporation

Part # P8XC151SA
Description  HIGH-PERFORMANCE CHMOS MICROCONTROLLER
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

P8XC151SA Datasheet(HTML) 9 Page - Intel Corporation

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8XC151SASB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
SIGNAL DESCRIPTIONS
Table 7 Signal Descriptions
Signal
Type
Description
Multiplexed
Name
With
A158
O
Address Lines
Upper address lines for the external bus
P270
AD70
IO
AddressData Lines
Multiplexed lower address lines and data lines
P070
for external memory
ALE
O
Address Latch Enable
ALE signals the start of an external bus
PROG
cycle and indicates that valid address information is available on lines
A158 and AD70 An external latch can use ALE to demultiplex the
address from the addressdata bus
CEX40
IO
Programmable Counter Array (PCA) InputOutput Pins
These
P163
are input signals for the PCA capture mode and output signals for the
P17
PCA compare mode and PCA PWM mode
EA
I
External Access
Directs program memory accesses to on-chip or
VPP
off-chip code memory For EA
e
0 all program memory accesses
are off-chip For EA
e
1 an access is to on-chip ROMOTPROM if
the address is within the range of the on-chip ROMOTPROM
otherwise the access is off-chip The value of EA
is latched at
reset For devices without on-chip ROMOTPROM EA
must be
strapped to ground
ECI
I
PCA External Clock Input
External clock input to the 16-bit PCA
P12
timer
INT10
I
External Interrupts 0 and 1
These inputs set bits IE10 in the TCON
P332
register If bits IT10 in the TCON register are set bits IE10 are set by
a falling edge on INT1
INT0
If bits INT10 are clear bits IE10
are set by a low level on INT10
PROG
I
Programming Pulse
The programming pulse is applied to this pin
ALE
for programming the on-chip OTPROM
P070
IO
Port 0
This is an 8-bit open-drain bidirectional IO port
AD70
P10
IO
Port 1
This is an 8-bit bidirectional IO port with internal pullups
T2
P11
T2EX
P12
ECI
P173
CEX30
CEX4
P270
IO
Port 2
This is an 8-bit bidirectional IO port with internal pullups
A158
The descriptions of A158P270 and AD70P070 are for the nonpage-mode chip configuration (compatible with
44-lead PLCC and 40-pin DIP MCS 51 microcontrollers) If the chip is configured for page-mode operation port 0 carries
the lower address bits (A70) and port 2 carries the upper address bits (A158) and the data (D70)
9


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