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EM78P447NAM Datasheet(PDF) 16 Page - ELAN Microelectronics Corp

Part # EM78P447NAM
Description  8-BIT MICRO-CONTROLLER
Download  57 Pages
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Manufacturer  EMC [ELAN Microelectronics Corp]
Direct Link  http://www.emc.com.tw
Logo EMC - ELAN Microelectronics Corp

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EM78P447N
OTP ROM
4.3 TCC/WDT & Prescaler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the
TCC or WDT only at any given time, and the PAB bit of the CONT register is used to determine the
prescaler assignment. The PSR0~PSR2 bits determine the ratio. The prescaler is cleared each time the
instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode,
are cleared by the “WDTC” or “SLEP” instructions. Fig. 6 depicts the circuit diagram of TCC/WDT.
• R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input
(edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at
every instruction cycle (without prescaler). Referring to Fig. 6, CLK=Fosc/2 or CLK=Fosc/4
selection is determined by the CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0",
and CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from external clock input, TCC
is increased by 1 at every falling edge or rising edge of TCC pin.
• The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after
the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode,
a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any
time during normal mode by software programming. Refer to WDTE bit of IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms
1 (default).
WDT
TE
TCC
8-bit Counter
2 cycles
TCC(R1)
SYNC
Pin
M
X
U
M
X
U
M
X
U
8-to-1 MUX
MUX
TS
0
PSR0~PSR2
WDT timeuot
PAB
TCC overflow interrupt
CLK(=Fosc/2)
PAB
(in IOCE)
WDTE
Data Bus
PAB
1
0
1
0
1
01
Fig. 6 TCC and WDT Block Diagram
1 <Note>: Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 19.6ms ± 30%
This specification is subject to change without prior notice.
10.21.2004 (V1.0)
16


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