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EM78P447NAM Datasheet(PDF) 18 Page - ELAN Microelectronics Corp |
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EM78P447NAM Datasheet(HTML) 18 Page - ELAN Microelectronics Corp |
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18 / 57 page  EM78P447N OTP ROM 4.5 RESET and Wake-up 1. RESET A RESET is initiated by one of the following events- (1) Power on reset, or (2) /RESET pin input “low”, or (3) WDT timeout. (if enabled) The device is kept in a RESET condition for a period of approx. 18ms 1 (one oscillator start-up timer period) after the reset is detected. Once the RESET occurs, the following functions are performed (refer to Fig.8). • The oscillator starts or is running • The Program Counter (R2) is set to all "1". • When power is switched on, bits 5~6 of R3 and the upper 2 bits of R4 are cleared. • All I/O port pins are configured as input mode (high-impedance state). • The Watchdog timer and prescaler are cleared. • Upon power on, the bits 5~6 of R3 are cleared. • Upon power on, the upper 2 bits of R4 are cleared. • The bits of CONT register are set to all "1" except bit 6 (INT flag). • IOCB register is set to ”1” (disable P60 ~ P67 wake-up function). • Bits 3 and 6 of IOCE register are cleared, and Bits 0, 4, and 5 are set to "1". • Bits 0 and 3 of R3F register and Bits 0 and 3 of IOCF registers are cleared. The sleep (power down) mode is asserted by executing the “SLEP” instruction. While entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by- (1) External reset input on /RESET pin; (2) WDT time-out (if enabled) 1 NOTE: Vdd = 5V, set up time period = 16.2ms ± 30% Vdd = 3V, set up time period = 19.6ms ± 30% This specification is subject to change without prior notice. 10.21.2004 (V1.0) 18 |
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