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EM78P447NAM Datasheet(PDF) 22 Page - ELAN Microelectronics Corp |
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EM78P447NAM Datasheet(HTML) 22 Page - ELAN Microelectronics Corp |
22 / 57 page ![]() EM78P447N OTP ROM Change ** To execute next instruction after the ”SLPC” bit status of IOCE register being on high-to-low transition. X: Not used. U: Unknown or don’t care. P: Previous value before reset. t: Check Table 5 2. The Status of RST, T, and P of STATUS Register A RESET condition is initiated by one of the following events: 1. A power-on condition, 2. A high-low-high pulse on /RESET pin, and 3. Watchdog timer time-out. The values of T and P (listed in Table 5 below) are used to verify the event that triggered the processor to wake up. Table 6 shows the events that may affect the status of T and P. Table 5 The Values of RST, T and P after RESET Reset Type T P Power on 1 1 /RESET during Operating mode *P *P /RESET wake-up during SLEEP1 mode 1 0 /RESET wake-up during SLEEP2 mode *P *P WDT during Operating mode 0 *P WDT wake-up during SLEEP1 mode 0 0 WDT wake-up during SLEEP2 mode 0 *P Wake-Up on pin change during SLEEP2 mode *P *P *P: Previous status before reset Table 6 The Events that may Affect the T and P Status Event T P Power on 1 1 WDTC instruction 1 1 WDT time-out 0 *P SLEP instruction 1 0 Wake-Up on pin change during SLEEP2 mode *P *P *P: Previous value before reset This specification is subject to change without prior notice. 10.21.2004 (V1.0) 22 |
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