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CAT1321LI-45TSSOP Datasheet(PDF) 6 Page - Catalyst Semiconductor |
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CAT1321LI-45TSSOP Datasheet(HTML) 6 Page - Catalyst Semiconductor |
6 / 18 page ![]() 6 CAT1320, CAT1321 Advance Information Doc. No. 25085, Rev. 00 When RESET I/O is driven to the active state, the 200 msec timer will begin to time the reset interval. If external reset is shorter than 200 ms, Reset outputs will remain active at least 200 ms. Glitches shorter than 100 ns on RESET input will not generate a reset pulse. Hardware Data Protection The CAT1320/21 family has been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. Whenever the device is in a Reset condition, the embedded EEPROM is disabled for all operations, including write operations. If the Reset output is active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal non-volatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before VCC reaches the minimum value of 2V. DEVICE OPERATION Reset Controller Description The CAT1320/21 precision Reset controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open- drain RESET/RESET outputs. During power-up, the RESET/RESET output remains active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset output. At this point the reset output will be pulled up or down by their respective pull up/down resistors. During power-down, the RESET/RESET output will be active when VCC falls below VTH. The RESET/RESET output will be valid so long as VCC is >1.0V (VRVALID). The device is designed to ignore the fast negative going VCC transient pulses (glitches). Reset output timing is shown in Figure 1. Manual Reset Operation The RESET pin can operate as reset output and manual reset input. The input is edge triggered; that is, the RESET input will initiate a reset timeout after detecting a high to low transition. Figure 1. RESET/RESET Output Timing GLITCH t VCC PURST t PURST t RPD t RVALID V V TH RESET RESET RPD t |
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