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54HCT00 Datasheet(HTML) 1 Page - Silicon Supplies

Part No. 54HCT00
Description  Low Power Schottky Logic
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Maker  SS [Silicon Supplies]
Homepage  https://siliconsupplies.com/

54HCT00 Datasheet(HTML) 1 Page - Silicon Supplies

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Quad 2-Input NAND Gates with LSTTL compatible inputs in bare die form
Rev 1.0
High Speed CMOS TTL Input – 54HCT00
Output Drive Capability: 10 LSTTL Loads
Low Input Current: 1µA
Outputs directly interface CMOS, NMOS and TTL
Operating Voltage Range: 4.5V to 5.5V
TTL / CMOS compatible Input Levels
Function compatible with 54LS00
Full Military Temperature Range.
Ordering Information
54HCT00 provides x4 independent 2-input NAND gates
performing the Boolean function Y = A • B or Y = A + B.
The device is fabricated using a 2.5µm 5V CMOS process
combining high speed LSTTL performance with CMOS low
power. Internal circuitry comprises of 3 stages and includes
buffered outputs for high noise immunity and stability.
Device inputs directly accept both standard CMOS and
LSTTL outputs. All inputs are equipped with protection
circuits against static discharge and transient excess
Die Dimensions in µm (mils)
The following part suffixes apply:
1250 (49)
No suffix - MIL-STD-883 /2010B Visual Inspection
“H” - MIL-STD-883 /2010B Visual Inspection
+ MIL-PRF-38534 Class H LAT
“K” - MIL-STD-883 /2010A Visual Inspection (Space)
+ MIL-PRF-38534 Class K LAT
LAT = Lot Acceptance Test.
For further information on LAT process flows see below.
Supply Formats:
Mechanical Specification
Default – Die in Waffle Pack (400 per tray capacity)
Die Size (Unsawn)
1250 x 350
49 x 53
Minimum Bond Pad Size
96 x 96
3.78 x 3.78
Die Thickness
350 (±20)
13.78 (±0.79)
Top Metal Composition
Al 1%Si 1.1µm
Back Metal Composition
N/A – Bare Si
Sawn Wafer on Tape – On request
Unsawn Wafer – On request
Die Thickness <> 350µm(14 Mils) – On request
Assembled into Ceramic Package – On request
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