A43E06161V-75 datasheet(9/46 Pages) AMICC

Part #	A43E06161V-75

Description	512K X 16 Bit X 2 Banks Synchronous DRAM

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Manufacturer	AMICC [AMIC Technology]

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A43E06161

PRELIMINARY

(July, 2005, Version 0.1)

8

AMIC Technology, Corp.

Simplified Truth Table

Command

CKEn-1 CKEn

CS

RAS CAS

WE

DQM

BA A10/

AP

A9~A0

Notes

Register

Mode Register Set

H

X

L

X

OP CODE

1,2

Auto Refresh

H

3

Entry

H

L

H

X

3

L

H

3

Refresh

Self

Refresh

Exit

L

H

X

3

Bank Active & Row Addr.

H

X

L

H

X

V

Row Addr.

4

Auto Precharge Disable

L

4

Read &

Column Addr. Auto Precharge Enable

H

X

L

H

L

H

X

V

H

Column

Addr.

4,5

Auto Precharge Disable

L

4

Write &

Column Addr. Auto Precharge Enable

H

X

L

H

L

X

V

H

Column

Addr.

4,5

Burst Stop

H

X

L

H

L

X

Bank Selection

V

L

Precharge

Both Banks

H

X

L

H

L

X

H

X

L

H

Entry

H

L

H

X

Clock Suspend or

Active Power Down

Exit

L

H

X

L

H

Entry

H

L

H

X

L

V

Precharge Power Down Mode

Exit

L

H

X

DQM

H

X

V

X

6

L

H

No Operation Command

H

X

H

X

7

Deep Power Down Entry

H

L

H

L

X

Deep Power Down Exit

L

H

X

7

(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)

Note :

1. OP Code : Operand Code

A0~A10/AP,BA : Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.

A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions as same as CBR refresh of DRAM.

The automatical precharge without Row precharge command is meant by “Auto”.

Auto/Self refresh can be issued only at both precharge state.

4. BA : Bank select address.

If “Low” at read, write, Row active and precharge, bank A is selected.

If “High” at read, write, Row active and precharge, bank B is selected.

If A10/AP is “High” at Row precharge, BA is ignored and both banks are selected.

5. During burst read or write with auto precharge, new read write command cannot be issued.

Another bank read write command can be issued at every burst length.

6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),

but makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)

7. After Deep Power Down mode exit, a full new initialization of the memory device is mandatory.

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