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A49FL004TL-33F Datasheet(PDF) 8 Page - AMIC Technology |
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A49FL004TL-33F Datasheet(HTML) 8 Page - AMIC Technology |
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8 / 36 page  A49FL004 PRELIMINARY (September, 2005, Version 0.0) 7 AMIC Technology, Corp. Table 2: FWH Read Cycle Figure 4: FWH Memory Read Cycle Waveforms CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 START IDSEL IMADDR IMSIZE TAR0 TAR1 RSYNC DATA TAR0 TAR1 FWH4 FWH[3:0] Clock Cycle Field FWH[3:0] Direction Descriptions 1 START 1101 IN Start of Cycle: “1101b” to indicate the start of a memory read cycle. FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transition high) should be recognized. The start field contents indicate and FWH read cycle. 2 IDSEL 0000 to 1111 IN ID Select Cycle: Indicates which FWH device should respond. If the IDSEL field matches the value set on ID[3:0] pins, then the particular FWH device will respond to subsequent commands. 3-9 IMADDR YYYY IN Address Cycle: This is the 28-bit memory address. The addressed transfer most-significant nibble first and least-significant nibble last. (i.e., a27-24 on FWH[3:0] first, and A3-A0 on FWH[3:0] last). 10 IMSIZE 0000 IN Memory Size Cycle: Indicates how many bytes will be or transferred during multi-byte operations. The A49FL004 only support “0000b” for one byte operation. 11 TAR0 1111 IN then Float Turn-Around cycle 0: The master (Intel ICH) has driven the bus to all”1”s and then float the bus. 12 TAR1 1111 (Float) Float then OUT Turn-Around cycle 1: The device takes control of the bus during this cycle. 13 RSYNC 0000 (READY) OUT Ready Sync: The FWH device indicates the least-significant nibble of data byte will be ready in next clock cycle. 14-15 DATA YYYY OUT Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on FWH[3:0] first, then I/O7 – I/O4 on FWH[3:0] last). 16 TAR0 1111 OUT then Float Turn-Around cycle 0: The FWH device has driven the bus to all “1”s and then float the bus. 17 TAR1 1111 (Float) Float then IN Turn-Around cycle 1: The master (Intel ICH) resumes control of the bus during this cycle. |
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