A49LF040TX-33 datasheet(8/31 Pages) AMICC

Part #	A49LF040TX-33

Description	4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory

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Manufacturer	AMICC [AMIC Technology]

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A49LF040

PRELIMINARY

(August, 2004, Version 0.1)

7

AMIC Technology, Corp.

Table 3: LPC Write Cycle

1. Field contents are valid on the rising edge of the present clock cycle.

LPC Write Waveforms

LCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

START

ADDRESS

TAR0

TAR1

SYNC

DATA

TAR0

TAR1

LFRAME#

LAD[3:0]

CYCTYPE

+ DIR

Clock

Cycle

Field

Name

Field Contents

LAD[3:0]

1

LAD[3:0]

Direction

Comments

1

START

0000

IN

LFRAME# must be active (low) for the part to respond. Only the last

start field (before LFRAME# transitioning high) should be

recognized.

2

CYCTYPE

+ DIR

010X

IN

Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle.

Bit 1 indicates the type of transfer “1” for Write. Bit 0 is reserved.

3-10

ADDRESS

YYYY

IN

Address Phase for Memory Cycle. LPC protocol supports a 32-bit

address phase. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first. See Table 4

for address bits definition and Table 5 for valid memory address

range.

11

DATA

ZZZZ

IN

This field is the least-significant nibble of the data byte.

12

DATA

ZZZZ

IN

This field is the most-significant nibble of the data byte.

13

TAR0

1111

IN

then Float

In this clock cycle, the host has driven the bus to all ‘1’s and then

floats the bus. This is the first part of the bus “turnaround cycle.”

14

TAR1

1111(float)

Float

then OUT

The A49LF040 takes control of the bus during this cycle.

15

SYNC

0000

OUT

The A49LF040 outputs the values 0000, indicating that it has

received data or a flash command.

16

TAR0

1111

OUT

then Float

In this clock cycle, the A49LF040 has driven the bus to all ‘1’s and

then floats the bus. This is the first part of the bus “turnaround

cycle.”

17

TAR1

1111(float)

Float

then IN

Host resumes control of the bus during this cycle.

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